Analysis
Design Analysis
ProtoFlow includes comprehensive design rule checking (DRC), electrical rule checking (ERC), topology analysis, and grid alignment validation to catch errors before they become problems.
# Design Rule Checks (DRC)
DRC validates the structural integrity of your schematic, checking for physical placement and connection issues.
Checks Performed
| Check | Severity | Description |
|---|---|---|
| Duplicate reference designators | Error | Two or more components share the same reference (e.g., two R1) |
| Wire touching unconnected pin | Warning | A wire passes near a pin but doesn't actually connect to it |
| Wire covering terminal | Warning | A wire overlaps a pin terminal, making the connection ambiguous |
| Overlapping components | Warning | Two components are placed on top of each other |
| Off-grid elements | Info | Components, wires, or pins that aren't aligned to the grid |
Running DRC
Run DRC from the toolbar or ask the AI Copilot to run it for you. Violations are highlighted directly on the canvas with hover tooltips showing the error details.
DRC results with error markers highlighted on the schematic canvas
# Electrical Rule Checks (ERC)
ERC validates the electrical connectivity of your schematic, checking for signal integrity and power distribution issues.
Checks Performed
| Check | Severity | Description |
|---|---|---|
| Floating pins | Error | Input pins that aren't connected to any net (may pick up noise) |
| Short circuits | Error | Multiple power nets connected together unintentionally |
| Output conflicts | Error | Multiple output drivers on the same net (bus contention) |
| No driver | Warning | A net with input pins but no output or power driver |
| Missing ground | Warning | Circuit has power symbols but no ground reference |
| Missing PWR_FLAG | Info | Power net without a PWR_FLAG to indicate power source |
ERC results highlighting floating pins and missing ground connections
# Grid Alignment Validation
Check for and fix off-grid elements to ensure clean connections and professional layouts.
Elements Checked
- Components — Component body positions
- Pins — Component pin positions
- Wires — Wire segment positions
- Wire endpoints — Start and end points of wires
- Labels — Net label positions
- Annotations — Text and shape annotation positions
- No-connect markers — No-connect symbol positions
Auto-Fix
The grid alignment tool can automatically snap all off-grid elements to the nearest grid intersection. Run it from the toolbar or ask the AI to "align everything to the grid."
# Topology Analysis
Analyze the high-level structure of your circuit to identify functional blocks and design patterns.
Analysis Capabilities
- Functional block detection — Automatically identifies distinct functional blocks (power supply, microcontroller section, sensor interface, etc.)
- Bypass capacitor grouping — Identifies which capacitors are associated with which ICs for decoupling
- Bus-connected component clustering — Groups components that share a common bus (SPI, I2C, etc.)
- Signal flow analysis — Traces signal paths through the circuit to understand data flow
- Component relationship analysis — Maps the connections between components to visualize the circuit hierarchy
Topology analysis overlay showing identified functional blocks with color-coded regions
Next Steps
- → Use Layout Automation to fix issues automatically
- → Export with File Management once checks pass